1. Field of the Invention
This invention is generally directed to an integrated circuit packaging configuration. More particularly, the invention relates to a high density interconnect structure and method for fabrication in which portions of dielectric or other materials are removed to create space for inserting an integrated circuit chip which may then be connected to the structure.
2. Description of the Related Art
In the packaging of very large scale integrated circuit devices, much space is taken up by mechanisms for connecting one chip to an adjacent device. This makes the packaging of integrated circuit devices and electronic components thereon larger than necessary. However, efforts expended in further developing these processes to further shrink the packaging have generally resulted in limited yield. Because a number of chips or dies on a wafer are often found to be defective, the number of wafers produced that are completely usable is generally lower than desired. Furthermore, there still exists the problem of interconnecting the chips of varying technologies on a single wafer. Accordingly, it would be very desirable to construct wafer scale integrated circuit packages using individual, easily testable integrated circuit chips. It is to this end that the invention is directed.
High density interconnect (HDI) techniques use a film overlay which covers a plurality of integrated circuit chips adjacent to one another on an underlying substrate. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of individual circuit chips. A significant advantage of the HDI technique is the ability to remove one or more of these interconnection layers so as to provide a multitude of arrangement and testing capabilities.
Methods for carrying out a multi-layer interconnect process using an overlay approach are described in commonly assigned U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in commonly assigned U.S. Pat. No. 4,933,042, issued Jun. 12, 1990, both of which are hereby incorporated by reference.
It is desirable to provide via openings or apertures in the polymer dielectric layer so as to be able to provide electrical connection between various parts of a chip or between several chips. Commonly assigned U.S. Pat. No. 4,894,115, issued Jan. 16, 1990, and commonly assigned U.S. Pat. No. 4,714,516, issued Dec. 22, 1987, which disclose embodiments for providing such apertures, are also hereby incorporated herein by reference.
Methods for gaining access to and replacing a defective integrated circuit chip are disclosed in commonly assigned U.S. Pat. No. 4,878,991, issued Nov. 7, 1989, which is also hereby incorporated by reference.
Future large volume module manufacturing requires further improvements in the existing process in several key areas including yield enhancement, cost reduction, and repairability. Mixed technologies of different materials such as Si and GaAs are difficult to integrate. Also, different chip suppliers sell chips of various dimensions with some thicknesses being in the 4 mil range and others in the 20 mil range. Rework of sensitive components is difficult and results in a higher cost integrated circuit package.
In HDI, polymers on sensitive chips decrease chip performance, so to keep their performance from degrading, ablation or removal of the dielectric overlay covering high frequency chips, electro-optical devices, or sensor chips is necessary. This step is very complicated and time consuming. Additionally, it creates a risk of degrading chip integrity and performance. Also, under conventional practices, the transition area from the edge of the milled pocket to the chip introduces a coupling of air and dielectric overlay which creates an impedance transition at radio frequencies that is difficult to characterize.